The invention relates to managing trace information storage using pipeline instruction insertion and filtering.
Processors can be configured to capture trace information, which can be used for testing and debugging of programs. For example, trace information can include a history of particular instructions that were executed in the pipeline of a processor for any number of processes or threads executing on that processor. The capture of trace information can generally be enabled or disabled. For a given thread, the trace information may include an entire instruction stream that includes every instruction that was executed in the lifetime of the thread and corresponding results, if any, for each instruction. Or, the trace information may include only selected instructions, from which other instructions that executed could be reconstructed if necessary. For example, to reduce the amount of information that needs to be stored to capture the trace information, the instruction stream can be filtered such that only instructions affecting control flow (e.g., branch instructions) and their resulting control flow changes (e.g., branch “taken,” or “not taken”), and certain other instructions that have dynamically determined results (e.g., load instructions and store instructions) are included. Whereas, instructions that do not affect control flow and whose results can be easily reconstructed from static analysis of the binary code for the original program (e.g., arithmetic operation instructions, such as add or subtract) are filtered out of the trace information. Other optimizations are also possible. For some processors, dedicated trace circuitry can be used to capture and store trace information during operation of a processor's pipeline.